The present invention relates generally to a method for writing data into a semiconductor memory device and more particularly to a method for writing data into a semiconductor memory device such as a SRAM (static random access memory) that may include a memory cell operating at a relatively low voltage.
It is a continuing goal to improve the bit density and decrease power consumption in a semiconductor memory device. One method of increasing the bit density is to decrease the size of the memory cell. In a SRAM (static random access memory), the size of the memory cell may be decreased by including memory cell transistors having a smaller size.
In order to decrease power consumption and improve breakdown reliability of memory cells having small sizes, memory cells receive a relatively low power supply voltage. For example, in a SRAM having memory cells configured with MOS (metal oxide semiconductor) transistors, the memory cells may operate using a power supply voltage as low as 1.2 V.
A configuration of a conventional SRAM will now be discussed.
FIG. 4 is a circuit schematic diagram illustrating a portion of a conventional SRAM given the general reference character 10.
Referring to FIG. 4, conventional SRAM 10 has a memory cell 20. Memory cell 20 stores a data logic value. Although not shown, conventional SRAM includes an array (matrix) of memory cells 20 arranged in rows and columns. Conventional SRAM 10 includes a write circuit 30 for writing data into memory cell 20. A word line WL is connected to a row of memory cells 20. Bit lines (BL0 and BL1) are connected to a column of memory cells 20 and write circuit 30. Although not shown, a plurality of bit lines and a plurality of word lines are included that respectively connect columns and rows of memory cells.
Memory cell 20 includes inverters (21 and 22) and transfer gates (Qn31 and Qn32). Inverter 21 has an input connected to node C2 and an output connected to node C1. Inverter 22 has an input connected to node C1 and an output connected to node C2. In this way, inverters (21 and 22) form a bi-stable flip-flop that stores a data value and inverted data value at respective nodes (C1 and C2).
Inverters (21 and 22) are CMOS (complementary MOS) type inverters. Inverter 21 includes a NMOS transistor Qn1 and a PMOS transistor Qp1. NMOS transistor Qn1 has a source connected to ground, a drain connected to node C1 and a gate connected to node C2. PMOS transistor Qp1 has a source connected to an array power supply, a drain connected to node C1 and a gate connected to node C2. Inverter 22 includes a NMOS transistor Qn2 and a PMOS transistor Qp2. NMOS transistor Qn2 has a source connected to ground, a drain connected to node C2 and a gate connected to node C1. PMOS transistor Qp2 has a source connected to an array power supply, a drain connected to node C2 and a gate connected to node C1.
Transfer gates (Qn31 and Qn32) may each be a NMOS transistor. Transfer gate Qn31 has a first source/drain terminal connected to bit line BL1, a second source/drain terminal connected to node C1, and a control gate connected to word line WL. Transfer gate Qn32 has a first source/drain terminal connected to bit line BL0, a second source/drain terminal connected to node C2, and a control gate connected to word line WL.
When data is written into memory cell 20, write circuit 30 applies a high voltage level to one bit line (BL0 and BL1) while applying a low level (ground or 0V) to the other bit line (BL0 or BL1) while a word line driver (not shown) applies a high potential to word line WL (thus selecting memory cell 20).
As an example, assuming data is stored in memory cell 20 so that node C1 has a high level and node C2 has a low level. A low level on node C2 is inverted by inverter 21 to keep node C1 high and the high level on node C1 is inverted by inverter 22 to keep node C2 low. In this way, the data is latched and stored in memory cell 20.
Now, assuming opposite data is written into memory cell 20. Word line WL is driven high, thus turning on transfer gates (Qn31 and Qn32). Write circuit 30 then applies a low level to bit line BL1 and a high level to bit line BL0. Because transfer gates (Qn31 and Qn32) are NMOS transistors, they provide an efficient pull down, but an inefficient pull up capability. Thus, the high level applied to bit line BL0 hardly contributes to the writing. The low level applied to bit line BL1 pulls node C1 towards the ground potential through transfer gate Qn31. Once node C1 is driven below a threshold voltage of inverter 22, inverter 22 pulls node C2 towards the high level.
When data is read from memory cell 20, word line WL is driven high and transfer gates (Qn31 and Qn32) are turned on. With transfer gates (Qn31 and Qn32) turned on, memory cell 20 will drive bit lines (BL0 and BL1) in accordance with a stored data value. For example, assuming node C1 is at a low level and node C2 is at a high level, the low level at node C1 pulls down bit line BL1 while bit line BL2 may remain at a precharged high level. The signals on bit lines (BL0 and BL1) are then amplified by a sense amplifier (not shown). In this way, data stored in memory cell 20 is read out and provided externally from conventional SRAM 10.
In a SRAM memory cell, a threshold voltage VTH of the NMOS transistors are set relatively high in order to prevent data from being disturbed due to noise. However, if the threshold voltage VTH is set too high, the time required for data to be written into the memory cell can become excessive. As an example, when the power supply voltage (VDD) of the memory cell array is 1.2 V, then the threshold voltage VTH is set to about 0.5 V.
When a conventional SRAM 10 as illustrated in FIG. 4 operates at a low power voltage (such as VDD=1.2V), any variations of applied signals from the power supply level or ground level can have considerable effects on the operation.
For example, assume data is to be written to memory cell 20 such that bit line BL0 is at a high level and bit line BL1 is at a low level. Word line WL is driven to a high level. However, due to a resistance of the bit line, the low level of bit line BL1 may be above the ground level. In this case, the current drive (pull down) of transfer gate Qn31 is reduced. Assuming memory cell 20 originally stored opposite data to what is being written, the potential at node C1 is determined by a ratio of the current drive (pull-up strength) of PMOS transistor Qp1 versus the current drive (pull-down strength) of transfer gate Qn31. With the current drive of transfer gate Qn31 reduced, the time required to switch node C1 from a high level to a low level can become excessive. Also, because inverter 22 drives node C2 based on the logic level of node C1, the time required to switch node C1 from a low level to a high level can also become excessive. Thus, the overall write cycle time of conventional SRAM 10 may be adversely affected.
FIG. 5 is a timing diagram illustrating writing data into memory cell 20 in conventional SRAM 10 under various conditions.
FIG. 5 includes a clock signal CLK (a timing clock necessary for the proper operation of the SRAM), word line WL signal, and bit line BL1 signal. Lines (C1 and C2) indicate signals at nodes (C1 and C2), respectively, when bit line BL1 is driven completely to the ground potential (0.0 V) during a write operation. Lines (C1xe2x80x2 and C2xe2x80x2) indicate signals at nodes (C1 and C2), respectively, when bit line BL1 is driven only to 0.2 V over the ground potential. In this case, the time (cell inversion time) between a mid-point (0.5 VDD) of a high transition of the word line WL and a 90 percent point (0.9 VDD) of a transition of node C2 (line C2xe2x80x2) to a high level is much longer than the case (line C2) when bit line BL1 is driven to the ground potential. If the potential of the low going bit line (in this case bit line BL1) is much higher than 0.2 V, the memory cell 20 may not even properly receive the write data.
As mentioned above, transistors in the SRAM cells are manufactured to be as small as reasonably possible in order to minimize the SRAM cell size to allow higher memory capacity and/or reduce chip size. However, when the transistor sizes are reduced, the transistor performance variations in transistor characteristics may increase. For example, an SRAM having a memory capacity of 1 Mbit may include a 5"sgr" Intrinsic Vth fluctuation among transistors, where "sgr" represents the standard deviation. In order to keep a sufficiently high yield, it is necessary to for the design to tolerate a 6"sgr" Intrinsic Vth fluctuation among transistors.
FIGS. 6 and 7 are graphs illustrating cell inversion times in an opposite data write in a memory cell for various power supply voltages versus a low (write) potential of a bit line. FIG. 6 illustrates a cell inversion time when there are no Intrinsic Vth fluctuation among transistors. FIG. 7 illustrates a cell inversion time when the Intrinsic Vth fluctuation among transistors is as much as 6"sgr", where "sgr" is 30 mV.
As shown in FIG. 6 (no Intrinsic Vth fluctuation), when the power supply (VDD) is 1.2 V, the time required for cell inversion (a 90 percent point (0.9 VDD) of a transition of node (N1 or N2) to a high level) is not unduly long as long as the potential VFL (bit line potential) is equal to or less than about 0.20 V. However, as illustrated in FIG. 7 (a 6"sgr" Intrinsic Vth fluctuation), when the power supply (VDD) is 1.2 V, the time required for cell inversion (a 90 percent point (0.9 VDD) of a transition of node (N1 or N2) to a high level) is unduly long even when the potential VFL (bit line potential) is about 0.05 V. As illustrated in FIGS. 6 and 7, the tolerance for variations in transistor performance when writing data into a memory cell is reduced. Thus, the yield of a conventional semiconductor device, such as a conventional SRAM 10 may decline.
In view of the above discussion, it would be desirable to provide a method for writing data into a semiconductor memory device in which data may be securely written into a memory cell and a semiconductor memory device therefore. It would also be desirable to provide the method in which data may not be disturbed even when the device operates using a low power voltage and a semiconductor memory device therefore.
According to the present embodiments, method of writing data into a semiconductor memory device including a memory cell to which a power supply potential and a ground potential are provided is disclosed. The method may include generating a negative voltage lower than the ground potential and providing complementary data signals to a bit line pair when writing data to a memory cell wherein the low one of the complementary data signals is essentially the negative voltage. In this way, compensation for a potential increment which may be caused due to a wiring resistance, or the like, of a bit line may be provided.
According to one aspect of the embodiments, a semiconductor memory device may include a memory cell to which a power supply potential and a ground potential are provided. A first and second bit line may be coupled to the memory cell. A method of writing data into the semiconductor memory device may include the steps of generating a negative voltage lower than the ground potential and providing complementary data signals to the first and second bit lines when writing data to the memory cell. The low one of the complementary data signals may be essentially the negative voltage.
According to another aspect of the embodiments, a method of writing data into the semiconductor memory device may include the step of providing the ground potential to the one of the first and second bit lines receiving the low one of the complementary data signals before providing the negative voltage.
According to another aspect of the embodiments, a semiconductor memory device may include a memory cell to which a power supply potential and a ground potential are provided. The memory cell may be coupled to a first and second bit line. A voltage dropping circuit may generate a negative voltage lower than the ground potential. A write circuit may provide complementary data signals to the first and second bit lines when writing data to the memory cell. The low one of the complementary data signals may be essentially the negative voltage.
According to another aspect of the embodiments, the memory cell may include a transfer gate that is turned on when data is being written to the memory cell and then turned off after the writing of data is completed. A precharge potential may be applied to the first and second bit lines after the transfer gate is turned off.
According to another aspect of the embodiments, the precharge potential may be essentially the power supply potential.
According to another aspect of the embodiments, the negative voltage may be less than or equal to a forward bias voltage of a PN junction.
According to another aspect of the embodiments, the semiconductor memory device may be a static random access memory (SRAM).
According to another aspect of the embodiments, a pulse delivering circuit may provide a low pulse when writing data into the memory cell. A capacitor may be coupled to receive the low pulse and provide the negative voltage.
According to another aspect of the embodiments, a semiconductor memory device may include an array of memory cells arranged into rows and columns. Each memory cell may receive a power supply potential and a ground potential. Each column of memory cells may be coupled to a first and second bit line. A write circuit may provide complementary data signals to the first and second bit lines coupled to a first one of the columns of memory cells when writing data to a first memory cell in the first one of the columns of memory cells. The low one of the complementary data signals may be a negative voltage below the ground potential.
According to another aspect of the embodiments, the write circuit may include a voltage dropping circuit. The voltage dropping circuit may provide the negative voltage to a predetermined one of the first and second bit lines in accordance with a data value to be written.
According to another aspect of the embodiments, a selector circuit may be coupled between the write circuit and a plurality of the columns of memory cells. The selector circuit may provide an electrical connection between the write circuit and the first one of the columns of memory cells during writing data to the first memory cell.
According to another aspect of the embodiments, the selector may provide the electrical connection in response to a predetermined address value.
According to another aspect of the embodiments, each of the memory cells may include a first insulated gate field effect transistor (IGFET) coupled to the first bit line and a second IGFET coupled to the second bit line. The first and second IGFETs may provide a data path to write data to the memory cell.
According to another aspect of the embodiments, each of the memory cells may further include first and second inverters forming a latch for storing a data value.
According to another aspect of the embodiments, the first and second IGFETs may be n-type IGFETs.